The terminals of an integrated circuit may be subject to accidental contact with electrically charged bodies during manufacture and assembly in a circuit complex or during operation such that potential differences of a very significant magnitude may be created. For example, a significant potential difference may be created between the gate electrodes of the input transistors, or between the drain regions of the output transistors and the substrate of semiconductor material on which the integrated circuit is formed. In the first case, if the potential differential exceeds the dielectric rigidity threshold of the gate insulation the transistor is put out of service by the electrostatic discharge that develops through the insulation. In the second case, a similar destructive effect occurs as soon as the potential difference exceeds the inverse breakdown threshold of the drain junction. By way of example, in a CMOS integrated circuit manufactured with 1.2 .mu.m technology the breakdown voltage for the input transistors is approximately 12 V to 14 V and that of the output transistors is approximately 12 V.
Various remedies are known for protecting the different input, output, and power supply terminals from electrostatic discharges. Some of them use resistors in series and diodes in series and/or in parallel and are integrated in the substrate on which the integrated circuit is formed to limit or shunt the currents resulting from the electrostatic discharges, thus lending themselves essentially to the protection of input terminals. Other remedies include use of structures of the thyristor discharge or Silicon Controlled Rectifier (SCR) type in parallel and can be used for the protection of both input and output terminals.
In many cases, protection devices using lateral bipolar transistors have also been used effectively.
A known protection device particularly suited for monolithic integration in a MOS integrated circuit to be protected is described in Italian patent application no. 26063 A/80 filed by this applicant. The protection device consists essentially of an NPN lateral transistor having an emitter and collector doped with N-type impurities simultaneously with, and identically to the source and drain regions of the IGFET of the MOS circuit to be protected, and an inaccessible base doped heavily and deeply with P-type impurities by ion implantation.
In Italian patent application no. 23077A/85 of this applicant, a perfected use of the same structure is described. The perfected protection device consists of a first and a second lateral bipolar transistor having their collector terminals connected respectively to the input terminal of the circuit and to the gate electrodes of the IGFET. The first and second bipolar transistors have their emitter terminals connected to a ground terminal and a diffuse resistor (R') connecting the collectors of the two lateral transistors.
The width of the base of the first transistor and the concentration of impurities in the bases of both transistors keep the ignition voltage of the negative resistance phenomena of the first lateral transistor, and the breakdown voltage of the second lateral transistor, at a value lower than the breakdown voltage of the gate insulating oxides and the breakdown voltage of the bipolar junctions included in the integrated circuit. The width of the base and the concentrations of the bases further keep the sustaining voltage of the first lateral transistor at a value higher than the supply voltage of the integrated circuit.
We shall now discuss specifically the protection requirement for the Vpp voltage supply terminals for non-volatile memory cell programming. As shown in FIG. 1, the ideal protection characteristic of a protection device for this type of voltage supply terminal should ignite by snap back at a voltage less than the breakdown voltage of the cell gate oxides, be able to sustain on voltages higher than the maximum rating of the supply terminal (13.2 V is typical for Vpp), and ensure static functionality following voltage spikes.
The methods of protection using lateral bipolar transistors usually implemented for the input/output terminals do not entirely satisfy the Vpp dedicated functionality requirements. For example, an 18 V trigger voltage is acceptable, but a 9 V sustaining voltage implies that in the case of ignition for a spike on Vpp the bipolar protection transistor would remain on because it is being fed by this power supply.
By applying special contrivances to the collector junction and using special process systems it is possible to obtain lateral bipolar transistors having acceptable clamp values and lateral bipolars with less doped collector scattering (n-) that typically display Vtrig=21-23 V and Vsu=14 V.
However, these solutions nevertheless have the following three shortcomings:
the protection structures are dependent on the particular device manufacturing process; PA0 the lateral bipolar transistors display deterioration after ESD because of charge being trapped in the "beak" of the oxide overlying the base region (soft leakage); and PA0 the trigger voltage is higher than the breakdown voltage of the n+junction towards the insulation system with less difference with respect to the Vbkdox voltage and the breakdown voltage of the gate insulating oxides.
Another bipolar solution with resistive divider displays the shortcoming of introducing a resistance in the path between the terminal pad and internal circuitry. Therefore, during memory cell programming it is possible that the necessary Vpp fraction on the cell gate is not available.